SDK • Re: IO_IRQ_BANK0 , SIO_IRQ_PROC0 or SIO_IRQ_PROC0 ?

Thanks for the clarification. That is what I suspected was happening.

I was led to believe there was a different treatment for GPIO in the following text. Also the texts you quote above also seemed to take care to carve out the possibility of an exception and seemed aimed to cater for the case of GPIOs having separate interrupts on each core.

There is one NVIC per core, and each core’s NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank.

Is that incorrect or am I misreading it?

Would it be possible to set a different ISR vector directly in the vector table for core1 ( accepting that I don't further use the SDK functions which may get tripped up by such direct interference) or is all that in the silicon?

Thanks.

Statistics: Posted by pie_face — Tue Jul 07, 2026 4:30 pm

---