Hello everyone.
I have a problem with DMA transfer from PIO to RAM in RPi5.
The PIO program, when triggered, is supposed to generate CLK signals and receive data from an external device. DMA should transfer this data from PIO buffers to RPi5 Host processor.
So something like that:Only for debugging purposes, I use push noblock PIO instruction. In this situation I even no need to reading data from PIO to HOST CPU.
I only requests PIO to read some samples from external device, using this:Then the PIO program simply generates CLK pulses, captures data from MISO line into its buffer, and nothing further happens with that data. And that's okay. The oscilloscope confirms that the PIO program generates as many CLK pulses as needed:
![Image]()
Then I move to the next step: program with push block:
This time I have to read data. I use:This version still works. But due to slow readings from main.c using pooling, i have delayed CLK packets:
![Image]()
PS. Oscilloscope timebase is different vs previous one.
First packets are fast, because of PIO FIFO buffers. Next are delayed because it have to wait intil push block instruction will pass it, and this is expected in this situation.
The ammount of CLK is correct, and received data values too.
Problem starts here, when I want to use DMA.
I use:I try this line after and before the PIO PIO triggering sequence. Without changes.
This is what I get:
![Image]()
or:
![Image]()
Sometimes transfers are divided into two parts, sometimes not. This will not be a problem for me if ammount of data and data values will be correct. But it wasn't.
The number of CLK pulses is not correct, indicating that DMA isn't performing enough reads. Additionally, the received data isn't correct. It's not just about missing the last reads, but gaps in the data appear anywhere (even the first 32-bit sample can be invalid). I also checked this for larger transfers (256, 512, 1024), and the amount of data read via DMA roughly keeps up with the requested amount, but it's not equal. Most data is correct, but incorrect reads appear at random positions (and subsequent data is shifted, so the order of data is incorrect).
For example, instead of reading:
0, 1, 2, 3, 4, 5, 6, 7
I get:
0, 1, scratch, 2, 3, 4. scratch
I cannot find root of this issue, so finally I post it here.
Can comebody help me with this?
Full project in attachement. Simple code, without interrupts, without threads, and without another PIO channels.
I have a problem with DMA transfer from PIO to RAM in RPi5.
The PIO program, when triggered, is supposed to generate CLK signals and receive data from an external device. DMA should transfer this data from PIO buffers to RPi5 Host processor.
So something like that:Only for debugging purposes, I use push noblock PIO instruction. In this situation I even no need to reading data from PIO to HOST CPU.
I only requests PIO to read some samples from external device, using this:
Code:
uint32_t samples_count = 32; pio_sm_clear_fifos(pio, sm); //pio_sm_xfer_data(pio, sm, PIO_DIR_FROM_SM, samples_count*4, in_buf); pio_sm_put(pio, sm, samples_count); pio_sm_exec(pio, sm, pio_encode_pull(true, true)); pio_sm_exec(pio, sm, pio_encode_mov(pio_y, pio_osr));
Then I move to the next step: program with push block:
This time I have to read data. I use:
Code:
for (uint32_t i2 = 0; i2 < samples_count; i2++) in_buf[i2] = pio_sm_get(pio, sm);
PS. Oscilloscope timebase is different vs previous one.
First packets are fast, because of PIO FIFO buffers. Next are delayed because it have to wait intil push block instruction will pass it, and this is expected in this situation.
The ammount of CLK is correct, and received data values too.
Problem starts here, when I want to use DMA.
I use:
Code:
pio_sm_xfer_data(pio, sm, PIO_DIR_FROM_SM, samples_count*4, in_buf);This is what I get:

or:

Sometimes transfers are divided into two parts, sometimes not. This will not be a problem for me if ammount of data and data values will be correct. But it wasn't.
The number of CLK pulses is not correct, indicating that DMA isn't performing enough reads. Additionally, the received data isn't correct. It's not just about missing the last reads, but gaps in the data appear anywhere (even the first 32-bit sample can be invalid). I also checked this for larger transfers (256, 512, 1024), and the amount of data read via DMA roughly keeps up with the requested amount, but it's not equal. Most data is correct, but incorrect reads appear at random positions (and subsequent data is shifted, so the order of data is incorrect).
For example, instead of reading:
0, 1, 2, 3, 4, 5, 6, 7
I get:
0, 1, scratch, 2, 3, 4. scratch
I cannot find root of this issue, so finally I post it here.
Can comebody help me with this?
Full project in attachement. Simple code, without interrupts, without threads, and without another PIO channels.
Statistics: Posted by say_amida — Tue Jun 09, 2026 8:20 pm




