UARTCLK is clk_peri, and PCLK is clk_sys - see the note at the end of 4.2 (just above the 4.2.1 heading) in the datasheet.
The ratio constraint is unlikely to bother you unless you are doing really odd things with the clock setup - clk_sys is normally the fastest clock in the system and clk_peri might sometimes be the same or else is slower - either way the constraint is satisfied.
The UART documentation (and, frankly the quality of the UART itself) suffers from the fact that they licenced the UART design from ARM rather than building their own.
The ratio constraint is unlikely to bother you unless you are doing really odd things with the clock setup - clk_sys is normally the fastest clock in the system and clk_peri might sometimes be the same or else is slower - either way the constraint is satisfied.
The UART documentation (and, frankly the quality of the UART itself) suffers from the fact that they licenced the UART design from ARM rather than building their own.
Statistics: Posted by arg001 — Tue Feb 27, 2024 4:17 pm